In recent years, practical use has been made about projector type graphic display devices using a light emitting element such as a laser diode (hereafter, referred to in abbreviation as “LD”) as a light source. In these projector type graphic display devices, video images are displayed on a screen by scanning and projecting a light beam emitted by the light source (laser beam light) by means of a scanning device such as a mirror. In order to represent gradation with such a graphic display device, the light beam from the light source must be modulated by some sort of means. One of such means is a method in which electric current driving a LD is directly controlled to modulate the light emission intensity of the LD.
On the other hand, when video signals are to be displayed on a display other than a CRT, so-called gamma correction should be performed to match light-emission brightness characteristics of the CRT In general, when the video signal level is represented by VIN, the gamma correction is performed such that the output brightness Lout is proportional to 2.2-th power of VIN. Therefore, in a projector using a LD as well, LD driving current must be supplied so as to be proportional to 2.2-th power of the video signal level VIN.
Generally, a LD emits a laser light beam when current higher than a certain value (threshold current) is caused to flow. However, it is known that, in LDS, the light output characteristics, in particular the threshold current with respect to drive current varies in accordance with changes in temperature or changes with time. Therefore, even if a LD is driven with constant current, the light emission intensity will vary along with variation of the threshold current.
For this reason, automatic power control (APC) is employed to control the amount of drive current by detecting the light emission intensity. In general, when the APC is employed in a graphic display device or an image write device, the APC is operated to adjust the amount of light during a non-display period (blanking period) contained in a video signal. During a video display period, an APC voltage detected during the blanking period is held by a hold circuit and control is performed so that a constant current is output from the LD drive circuit.
Referring to FIG. 16, description will be made of a conventional current output type digital-analog conversion circuit capable of performing gamma correction. The illustrated gamma-corrected current output digital-analog conversion circuit is composed of a look-up table 101, a bit conversion circuit 102, a binary current generator 103, and a reference current circuit 104.
The look-up table 101 describes an m-bit data pattern corresponding to an n-bit data pattern, satisfying the relationship of m>n. The bit conversion circuit 102 refers to the look-up table 101 and converts the n-bit input digital data D0 to D(n−1) into m-bit data D0 to D(m−1). The binary current generator 103 outputs a current IDAC which increases in a binary manner according to the input digital data. The reference current circuit 104 supplies the binary current generator 103 with a reference current IREF which serves as a reference for an output current IDAC of the binary current generator 103 and is adjustable by a control signal CNT.
The circuit shown in FIG. 16 performs gamma correction in the following procedures. The m-bit output data described in the look-up table 101 assume values proportional to 2.2-th powers of the n-bit input data. Accordingly, the n-bit input digital data D0 to D(n−1) is converted into gamma-corrected m-bit data D0 to D(m−1) by the bit conversion circuit 102, and thus a gamma-corrected output current IDAC can be output from the binary current generator 103.
FIG. 17 shows a LD drive circuit using this gamma-corrected current output digital-analog conversion circuit. This LD current drive circuit is composed of a gamma-corrected current output digital-analog circuit 112, a bias current output circuit 119, an adder 120, a drive current output unit 113, a LD 114, a light intensity detector 115, a comparator 117, and a sample hold circuit (S/H) 118.
The gamma-corrected current output digital-analog circuit 112 outputs a gamma-corrected output current IDAC. The bias current output circuit 119 outputs a bias current IBIAS which is adjustable by a control signal CNT0. The adder 120 adds up the current IDAC and the bias current IBIAS. The drive current output unit 113 outputs a drive current IOUT. The LD 114 outputs laser light according to the drive current IOUT. The light intensity detector 115 detects the intensity of light output by the LD 114 and outputs a detection voltage DET The comparator 117 compares the detection voltage DET with a reference voltage VREF and outputs a difference voltage. The sample hold circuit 118 sample-holds the output voltage of the comparator 117.
The LD current drive circuit shown in FIG. 17 performs APC in the following procedures. In the first place, predetermined input data is input to the gamma-corrected current output DAC circuit 112, and the LD 114 is driven at a certain current value. The light intensity detector 115 detects the intensity of the light thus output by the LD 114 and outputs a detection voltage DET of a certain value. The comparator 117 compares the detection voltage value DET with the reference voltage VREF1 or VREF2, and outputs a difference voltage.
This difference voltage is fed back, via the sample hold circuit 118, as a control signal CNT0 for adjusting the output current IBIAS of the bias current output circuit 119 and as a control signal CNT1 for adjusting the output current IDAC of the gamma-corrected current output DAC 112. Eventually, the detection voltage DET output by the light intensity detector 115 becomes equal to the reference voltage VREF1 or VREF2, and the LD 114 emits light at a desired intensity in accordance with the predetermined input data. This makes it possible to prevent the LD from varying its output light intensity due to variation of the threshold current.
In contrast, in the LD drive circuit using a gamma-corrected current output digital-analog conversion circuit, shown in FIG. 16, only two current values, namely a bias current IBIAS and a reference current IREF are set by the APC control. This means that the APC control is not conducted on any current corresponding to intermediate gradation, which makes it difficult to perform precise gamma correction. In addition, a look-up table and a bit conversion circuit are required to perform gamma correction.
A gamma-corrected current output digital-analog conversion circuit to solve this problem is proposed in Patent Document 1 (Japanese Laid-Open Patent Publication NO. 2004-112183, page 20, FIG. 4). The current output type digital-analog conversion circuit proposed in FIG. 4 of Patent Document 1 is shown in FIG. 18 attached herein. This current output type digital-analog conversion circuit is composed of a decoder 81 and a conversion unit 82. The conversion unit 82 has a plurality of current adding type DACs 82-1, 82-2, . . . 82-k (k in number in the example shown in FIG. 18).
Each signal group output by the decoder 81 shown in FIG. 18 contains data of 2mi−1 fixed increments corresponding to higher-order mi bits, data of ni binary increments corresponding to lower-order ni bits, and data of a carrier bit. For example, in the data input to a current adding type DACi, the data DBi0 to DBi(ni−1) are data corresponding to the lower-order ni binary increments, the data DAi1 to DAi(2mi−1) are data corresponding to the higher-order (2mi−1) fixed increments, and the data CRYi is carrier data.
The data DBi0 to DBi(ni−1) corresponding to the lower-order ni binary increments is capable of outputting a current of up to (2ni−1) times as high as one LSB, the minimum unit of output current. The data DAi1 to DAi (2mi−1) corresponding to the higher-order (2mi−1) fixed increments is capable of varying the output current by one unit at a time, the unit being defined by the current corresponding to 2ni LSB. The carrier bit CRYi is capable of controlling the current output corresponding to one LSB. It should be noted that, herein, i=1, 2, . . . , k.
The current output of the current adding type DAC1 to DACk shown in FIG. 18 will be described, using a specific data example. It is assumed here that 8-bit data DIN, for example, is input to the decoder 81 as image data. The conversion unit 82 converts the 8-bit image data DIN into a current IOUT by means of three current adding type DACs, DAC1, DAC2 and DAC3. This means that k=3 in the conversion unit 82 shown in FIG. 18. It is also assumed that the DAC1 and the DAC2 are 6-bit DACs, while the DAC3 is a 7-bit DAC. Adding these three DACs, 26+26+27=28 is obtained, and hence an 8-bit DAC is obtained. It is assumed that bits of the image data DIN input to the decoder 81 consist of DI7 (MSB) to DI0 (LSB).
FIGS. 19, 20 and 21 show codes output by the decoder 81 when the 8-bit data DI7 to DI0 is input as described in the above. In this case, the DAC1 receives input of lower-order 4-bit data DB10 to DB13, decode signals DA11 to DA13 for the higher-order two bits in the six bits, and the carrier CRY1. The DAC2 receives input of lower-order 4-bit data DB20 to DB23, decode signals DA21 to DA23 for the higher-order two bits in the six bits, and the carrier CRY2. The DAC3 receives input of lower-order 4-bit data DB30 to DB33, decode signals DA31 to DA37 for the higher-order three bits in the seven bits, and the carrier CRY3.
Hereafter, description will be made of respective output currents from the DAC1 to DAC3 in sequence. The 8-bit input data DI7 to DI0 assume an arbitrary value within the range of 0 to 255. The decoder 81 controls the signal group output to the DAC1 to DAC3 in accordance with the values of the input data DI7 to DI0. The DAC1 to DAC3 perform different operations from each other in accordance with the values of the input data DI7 to DI0.
First, description will be made of operations of the DAC1 to DAC3 in accordance with the values of DI7 and DI6. When the input data DI7 to DI0 are from 0 to 63, that is, when DI7=L and DI6=L, the DAC1 performs DAC intrinsic operation. When the input data are from 64 to 255, that is, when the conditions of DI7=L and DI6=L are not satisfied, output currents of the DAC1 corresponding to 64 LSB are all turned ON. This means that, in this case, the DAC1 outputs a current IO1 corresponding to 64 LSB.
As for the DAC2, when the input data DI7 to DI0 are from 0 to 63, that is, when 17=L and DI6=L, output currents of the DAC2 corresponding to 64 LSB are all turned OFF. This means that, in this case, the output current IO2 from the DAC2 is zero. When the input data are from 64 to 127, that is, when DI7=L and DI6=H, the DAC2 performs DAC intrinsic operation. Further, when the input data are from 128 to 255, that is, when DI7=H, output current of the DAC2 corresponding to 64 LSB are all turned ON. This means that, in this case, the DAC2 outputs a current IO2 corresponding to 64 LSB.
As for the DAC3, when the input data are from 0 to 127, that is, when DI7=L, output currents of the DAC3 corresponding to 127 LSB are all turned OFF, This means that, in this case, the output current IO3 from the DAC3 is zero. When the input data are from 128 to 255, that is, when DI7=H, the DAC3 performs DAC intrinsic operation.
In the current output type digital-analog conversion circuit described in FIG. 4 of Patent Document 1, as described above, the gamma curve is divided into a plurality of regions, and the current adding type DACs 82-1 to 82-k are arranged in the plurality of regions, respectively. The current adding type DACs are controlled to assume the non-output state, the normal output state, and the full-output state. The respective current adding type DACs generate reference currents IREF1 to IREFk corresponding to one LSB or a predetermined multiple thereof by using the reference current source, and output a current including the carry in accordance with the input data from the decoder 81.
The current adding type DACs add up and output currents according to the codes corresponding to the fixed increments of the higher-order mi (i=1 to k) bits and the binary increments of the lower-order ni bits generated in accordance with the input data DIN. Further, the currents generated by the current adding type DACs in the respective regions are added up to obtain the total output current IOUT. This configuration makes it possible to supply a drive current which is gamma-corrected without the look-up table or the bit conversion circuit.
FIG. 23 shows a LD drive circuit employing the current output type digital-analog conversion circuit described in FIG. 4 of Patent Document 1. The LD drive circuit shown in FIG. 23 performs APC control on the reference currents IREF1 to IREFk of the reference current source 130. Since the APC control thus can be performed also on the currents corresponding to intermediate gradation, precise gamma correction can be performed.